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? semiconductor components industries, llc, 2000 november, 2000 rev. 6 1 publication order number: mmdf2c01hd/d mmdf2c01hd preferred device power mosfet 2 amps, 12 volts complementary so8, dual these miniature surface mount mosfets feature ultra low r ds(on) and true logic level performance. they are capable of withstanding high energy in the avalanche and commutation modes and the drain tosource diode has a very low reverse recovery time. minimos de- vices are designed for use in low voltage, high speed switching applications where power efficiency is important. typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. they can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. ? ultra low r ds(on) provides higher efficiency and extends battery life ? logic level gate drive can be driven by logic ics ? miniature so8 surface mount package saves board space ? diode is characterized for use in bridge circuits ? diode exhibits high speed, with soft recovery ? i dss specified at elevated temperature ? mounting information for so8 package provided maximum ratings (t j = 25 c unless otherwise noted) (note 1.) rating symbol value unit draintosource voltage nchannel pchannel v dss 20 12 vdc gatetosource voltage v gs 8.0 vdc drain current continuous nchannel pchannel pulsed nchannel pchannel i d i dm 5.2 3.4 48 17 a operating and storage temperature range t j and t stg 55 to 150 c total power dissipation @ t a = 25 c (note 2.) p d 2.0 watts thermal resistance junction to ambient (note 2.) r q ja 62.5 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds. t l 260 c 1. negative signs for pchannel device omitted for clarity. 2. mounted on 2o square fr4 board (1o sq. 2 oz. cu 0.06o thick single sided) with one die operating, 10 sec. max. nsource 1 2 3 4 8 7 6 5 top view ngate psource pgate ndrain ndrain pdrain pdrain 2 amperes 12 volts r ds(on) = 45 m (nchannel) r ds(on) = 180 m (pchannel) device package shipping ordering information mmdf2c01hdr2 so8 2500 tape & reel http://onsemi.com d s g pchannel d s g nchannel so8, dual case 751 style 14 lyww marking diagram d2c01 l = location code y = year ww = work week pin assignment 1 8 preferred devices are recommended choices for future use and best overall value.
mmdf2c01hd http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) (note 1.) characteristic symbol polarity min typ max unit off characteristics drainsource breakdown voltage (v gs = 0 vdc, i d = 250 m adc) v (br)dss (n) (p) 20 12 vdc zero gate voltage drain current (v gs = 0 vdc, v ds = 20 vdc) (v gs = 0 vdc, v ds = 12 vdc) i dss (n) (p) 1.0 1.0 m adc gatebody leakage current (v gs = 8.0 vdc, v ds = 0) i gss 100 nadc on characteristics (note 3.) gate threshold voltage (v ds = v gs , i d = 250 m adc) v gs(th) (n) (p) 0.7 0.7 0.8 1.0 1.1 1.1 vdc draintosource onresistance (v gs = 4.5 vdc, i d = 4.0 adc) (v gs = 4.5 vdc, i d = 2.0 adc) r ds(on) (n) (p) 0.035 0.16 0.045 0.18 ohm draintosource onresistance (v gs = 2.7 vdc, i d = 2.0 adc) (v gs = 2.7 vdc, i d = 1.0 adc) r ds(on) (n) (p) 0.043 0.2 0.055 0.22 ohm forward transconductance (v ds = 2.5 adc, i d = 2.0 adc) (v ds = 2.5 adc, i d = 1.0 adc) g fs (n) (p) 3.0 3.0 6.0 4.75 mhos dynamic characteristics input capacitance c iss (n) (p) 425 530 595 740 pf output capacitance (v ds = 10 vdc, v gs = 0 vdc, f = 1.0 mhz) c oss (n) (p) 270 410 378 570 transfer capacitance ) c rss (n) (p) 115 177 230 250 switching characteristics (note 4.) turnon delay time (v dd = 6.0 vdc, i d = 4.0 adc, t d(on) (n) (p) 13 21 26 45 ns rise time (v dd 6 . 0 vdc , i d 4 . 0 adc , v gs = 2.7 vdc, r g = 2.3 w ) t r (n) (p) 60 156 120 315 turnoff delay time (v dd = 6.0 vdc, i d = 2.0 adc, v gs = 2.7 vdc, t d(off) (n) (p) 20 38 40 75 fall time v gs = 2 . 7 vdc , r g = 6.0 w ) t f (n) (p) 29 68 58 135 turnon delay time (v ds = 6.0 vdc, i d = 4.0 adc, t d(on) (n) (p) 10 16 20 35 rise time (v ds 6 . 0 vdc , i d 4 . 0 adc , v gs = 4.5 vdc, r g = 2.3 w ) t r (n) (p) 42 44 84 90 turnoff delay time (v ds = 6.0 vdc, i d = 2.0 adc, v gs = 4.5 vdc, t d(off) (n) (p) 24 68 48 135 fall time v gs = 4 . 5 vdc , r g = 6.0 w ) t f (n) (p) 28 54 56 110 1. negative signs for pchannel device omitted for clarity. 3. pulse test: pulse width 300 m s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperature.
mmdf2c01hd http://onsemi.com 3 electrical characteristics continued (t a = 25 c unless otherwise noted) (note 1.) characteristic symbol polarity min typ max unit switching characteristics continued (note 4.) total gate charge q t (n) (p) 9.2 9.3 13 13 nc gatesource charge (v ds = 10 vdc, i d = 4.0 adc, v gs = 4.5 vdc) q 1 (n) (p) 1.3 0.8 gatedrain charge (v ds = 6.0 vdc, i d = 2.0 adc, v gs = 4.5 vdc ) q 2 (n) (p) 3.5 4.0 v gs = 4 . 5 vdc) q 3 (n) (p) 3.0 3.0 sourcedrain diode characteristics (t c = 25 c) forward voltage (note 3.) (i s = 4.0 adc, v gs = 0 vdc) (i s = 2.0 adc, v gs = 0 vdc) v sd (n) (p) 0.95 1.69 1.1 2.0 vdc reverse recovery time t rr (n) (p) 38 48 ns ( i f = i s , t a (n) (p) 17 23 (i f = i s , di s /dt = 100 a/ m s) t b (n) (p) 22 25 reverse recovery stored charge q rr (n) (p) 0.028 0.05 m c 1. negative signs for pchannel device omitted for clarity. 3. pulse test: pulse width 300 m s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperature.
mmdf2c01hd http://onsemi.com 4 typical electrical characteristics 0 0.4 0.8 t j = 25 c 1.2 1.6 2 4.5 v 0.2 0.6 1 1.4 1.8 v gs = 8 v 3.1 v 2.7 v 2.5 v 2.3 v 2.1 v 1.9 v 1.5 v 1.7 v 1.3 v 0 0.4 0.8 1.2 1.6 2 0.2 0.6 1 1.4 1.8 0 2 4 8 6 v ds , drain-to-source voltage (volts) figure 1. onregion characteristics i d , drain current (amps) nchannel pchannel 1 1.2 1.4 2.2 i d , drain current (amps) v gs , gate-to-source voltage (volts) figure 2. transfer characteristics v ds 10 v 1.6 1.8 2 0 2 4 8 6 25 c 100 c t j = -55 c 0 0.4 0.8 0 1 2 4 t j = 25 c 1.2 4.5 v 3 1.6 2 3.1 v v gs = 8 v 1.5 v 2.5 v v ds , drain-to-source voltage (volts) figure 1. onregion characteristics i d , drain current (amps) 1.7 v 0.2 0.6 1 1.4 1.8 1.9 v 2.1 v 2.3 v 2.7 v 1 1.2 1.4 2.8 i d , drain current (amps) v gs , gate-to-source voltage (volts) figure 2. transfer characteristics v ds 10 v 1.6 1.8 2 0 1 2 4 3 25 c 100 c t j = -55 c 2.2 2.4 2.6
mmdf2c01hd http://onsemi.com 5 typical electrical characteristics nchannel pchannel t j = 25 c v gs = 2.7 v 4.5 v r ds(on) , drain-to-source resistance (normalized) r ds(on) , drain-to-source resistance (ohms) 024 8 0.03 0.04 0.05 0.06 0.07 024 8 0.030 0.035 0.040 0.050 v gs , gate-to-source voltage (volts) figure 3. onresistance versus gatetosource voltage i d , drain current (amps) figure 4. onresistance versus drain current and gate voltage t j , junction temperature ( c) figure 5. onresistance variation with temperature t j = 25 c i d = 2 a 6 -50 -25 0 25 50 75 100 125 150 r ds(on) , drain-to-source resistance (ohms) 0.045 6 r ds(on) , drain-to-source resistance (ohms) 024 8 0.1 0.20 0.25 0.30 0.35 v gs , gate-to-source voltage (volts) t j = 25 c i d = 1 a 6 0.15 figure 3. onresistance versus gatetosource voltage 0 0.8 1.6 4 0.10 0.15 0.20 0.30 i d , drain current (amps) figure 4. onresistance versus drain current and gate voltage t j = 25 c v gs = 2.7 v 4.5 v r ds(on) , drain-to-source resistance (ohms) 0.25 2.4 3.2 r ds(on) , drain-to-source resistance (normalized) t j , junction temperature ( c) figure 5. onresistance variation with temperature -50 -25 0 25 50 75 100 125 150 0 0.5 1 2 1.5 v gs = 4.5 v i d = 2 a 0 0.5 1 2 1.5 v gs = 4.5 v i d = 4 a
mmdf2c01hd http://onsemi.com 6 typical electrical characteristics nchannel pchannel 024 12 100 v ds , drain-to-source voltage (volts) figure 6. draintosource leakage current versus voltage i dss , leakage (na) v gs = 0 v t j = 125 c 10 810 100 c 6 04 12 1000 v ds , drain-to-source voltage (volts) figure 6. draintosource leakage current versus voltage i dss , leakage (na) v gs = 0 v t j = 125 c 100 8 10 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge con- trolled. the lengths of various switching intervals ( d t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calcu- lating rise and fall because draingate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average in- put current (i g(av) ) can be made from a rudimentary analy- sis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resis- tive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turnon and turnoff delay times, gate current is not constant. the simplest calculation uses appropriate val- ues from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the offstate condition when cal- culating t d(on) and is read at a voltage corresponding to the onstate when calculating t d(off) . at high switching speeds, parasitic circuit elements com- plicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a func- tion of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to mea- sure and, consequently, is not specified. the resistive switching time variation versus gate resis- tance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an opti- mally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses.
mmdf2c01hd http://onsemi.com 7 nchannel pchannel 400 800 1200 2000 1600 80 812 v gs v ds 44 t j = 25 c c iss c oss c rss v ds = 0 v v gs = 0 v 0 c iss c rss gate-to-source or drain-to-source voltage (volts) c, capacitance (pf) figure 7. capacitance variation figure 8. gatetosource and draintosource voltage versus total charge r g , gate resistance (ohms) 0.1 10 100 100 10 1 t, time (ns) v dd = 6 v i d = 4 a v gs = 4.5 v t j = 25 c t r t f t d(off) t d(on) figure 9. resistive switching time variation versus gate resistance 10 v gs , gate-to-source voltage (volts) 8 6 4 2 0 0 4 2 0 q t , total charge (nc) v ds , drain-to-source voltage (volts) 5 3 1 24 6 810 i d = 4 a t j = 25 c v ds v gs q2 q3 q1 1 qt 400 800 1200 2000 1600 80 812 v gs v ds 44 t j = 25 c v ds = 0 v v gs = 0 v 0 c rss c iss c oss c rss c iss gate-to-source or drain-to-source voltage (volts) c, capacitance (pf) figure 7. capacitance variation figure 8. gatetosource and draintosource voltage versus total charge 10 v gs , gate-to-source voltage (volts) 8 6 4 2 0 0 4 2 0 q t , total charge (nc) v ds , drain-to-source voltage (volts) 5 3 1 246810 i d = 2 a t j = 25 c v ds v gs qt q2 q3 q1 r g , gate resistance (ohms) 1 10 100 1000 100 10 t, time (ns) v dd = 6 v i d = 2 a v gs = 4.5 v t j = 25 c t r t f t d(off) t d(on) figure 9. resistive switching time variation versus gate resistance
mmdf2c01hd http://onsemi.com 8 draintosource diode characteristics the switching characteristics of a mosfet body diode are very important in systems using it as a freewheeling or commutating diode. of particular interest are the reverse re- covery characteristics which play a major role in determin- ing switching losses, radiated noise, emi and rfi. system switching losses are largely due to the nature of the body diode itself. the body diode is a minority carrier de- vice, therefore it has a finite reverse recovery time, t rr , due to the storage of minority carrier charge, q rr , as shown in the typical reverse recovery wave form of figure 14. it is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. obviously, repeatedly forcing the diode through reverse recovery fur- ther increases switching losses. therefore, one would like a diode with short t rr and low q rr specifications to minimize these losses. the abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ring- ing. the mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high di/dts. the diode's negative di/dt during t a is directly con- trolled by the device clearing the stored charge. however, the positive di/dt during t b is an uncontrollable diode charac- teristic and is usually the culprit that induces current ringing. therefore, when comparing diodes, the ratio of t b /t a serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. a ratio of 1 is considered ideal and values less than 0.5 are considered snappy. compared to on semiconductor standard cell density low voltage mosfets, high cell density mosfet diodes are faster (shorter t rr ), have less stored charge and a softer re- verse recovery characteristic. the softness advantage of the high cell density diode means they can be forced through re- verse recovery at a higher di/dt than a standard cell mos- fet diode without increasing the current ringing or the noise generated. in addition, power dissipation incurred from switching the diode will be less due to the shorter re- covery time and lower switching losses. nchannel pchannel v gs = 0 v t j = 25 c 0.3 0.4 0.5 0.6 0.7 0 1 2 v sd , source-to-drain voltage (volts) figure 10. diode forward voltage versus current i s , source current (amps) 0.8 0.9 3 4 v gs = 0 v t j = 25 c 1 0.4 0.6 0.8 1 1.2 0 0.5 1 v sd , source-to-drain voltage (volts) figure 10. diode forward voltage versus current i s , source current (amps) 1.4 1.8 1.5 2 v gs = 0 v t j = 25 c 1.6
mmdf2c01hd http://onsemi.com 9 i s , source current t, time figure 11. reverse recovery time (t rr ) di/dt = 300 a/ m s standard cell density high cell density t b t rr t a t rr safe operating area the forward biased safe operating area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is for- ward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak re- petitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, atransient thermal resistance gen- eral data and its use.o switching between the offstate and the onstate may tra- verse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded, and that the transition time (t r , t f ) does not exceed 10 m s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) t c )/(r q jc ). a power mosfet designated efet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating condi- tions differing from those specified. although industry prac- tice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junc- tion temperature. figure 12. maximum rated forward biased safe operating area figure 12. maximum rated forward biased safe operating area 0.1 v ds , drain-to-source voltage (volts) 1 10 i d , drain current (amps) r ds(on) limit thermal limit package limit 0.01 v gs = 8 v single pulse t c = 25 c 10 0.1 dc 10 ms 1 100 100 mounted on 2" sq. fr4 board (1" sq. 2 oz. cu 0.06" thick single sided) with one die operating, 10s max. 1 ms 0.1 v ds , drain-to-source voltage (volts) 1 10 i d , drain current (amps) r ds(on) limit thermal limit package limit 0.01 v gs = 20 v single pulse t c = 25 c 10 0.1 dc 10 ms 1 100 100 mounted on 2" sq. fr4 board (1" sq. 2 oz. cu 0.06" thick single sided) with one die operating, 10s max. 1 ms 100 m s 10 m s nchannel pchannel
mmdf2c01hd http://onsemi.com 10 typical electrical characteristics figure 13. thermal response figure 14. diode reverse recovery waveform di/dt t rr t a t p i s 0.25 i s time i s t b t, time (s) rthja(t), effective transient thermal resistance 1 0.1 0.01 d = 0.5 single pulse 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 0.2 0.1 0.05 0.02 0.01 1.0e+02 1.0e+03 0.001 10 0.0175 w 0.0710 w 0.2706 w 0.5776 w 0.7086 w 107.55 f 1.7891 f 0.3074 f 0.0854 f 0.0154 f chip ambient normalized to q ja at 10s.
mmdf2c01hd http://onsemi.com 11 information for using the so8 surface mount package minimum recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to ensure proper solder connection inter- face between the board and the package. with the correct pad geometry, the packages will selfalign when subjected to a solder reflow process. mm inches 0.060 1.52 0.275 7.0 0.024 0.6 0.050 1.270 0.155 4.0 so8 power dissipation the power dissipation of the so8 is a function of the in- put pad size. this can vary from the minimum pad size for soldering to the pad size given for maximum power dissipa- tion. power dissipation for a surface mount device is deter- mined by t j(max) , the maximum rated junction temperature of the die, r q ja , the thermal resistance from the device junction to ambient; and the operating temperature, t a . us- ing the values provided on the data sheet for the so8 package, p d can be calculated as follows: p d = t j(max) t a r q ja the values for the equation are found in the maximum ratings table on the data sheet. substituting these values into the equation for an ambient temperature t a of 25 c, one can calculate the power dissipation of the device which in this case is 2.0 watts. p d = 150 c 25 c 62.5 c/w = 2.0 watts the 62.5 c/w for the so8 package assumes the recom- mended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 watts using the footprint shown. another alternative would be to use a ceramic sub- strate or an aluminum core board such as thermal clad . using board material such as thermal clad, the power dis- sipation can be doubled using the same footprint. soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are sub- jected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference shall be a maximum of 10 c. ? the soldering temperature and time shall not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient shall be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied during cooling. * soldering a device without preheating can cause exces- sive thermal shock and stress which can result in damage to the device.
mmdf2c01hd http://onsemi.com 12 typical solder heating profile for any given circuit board, there will be a group of control settings that will give the desired heat pattern. the operator must set temperatures for several heating zones and a figure for belt speed. taken together, these control settings make up a heating aprofileo for that particular circuit board. on machines controlled by a computer, the computer remembers these profiles from one operating session to the next. figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. this profile will vary among soldering systems, but it is a good starting point. factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. this profile shows tempera- ture versus time. the line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. the two profiles are based on a high density and a low density board. the vitronics smd310 convection/infrared reflow soldering system was used to generate this profile. the type of solder used was 62/36/2 tin lead silver with a melting point between 177189 c. when this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. the components on the board are then heated by conduction. the circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. step 1 preheat zone 1 arampo step 2 vent asoako step 3 heating zones 2 & 5 arampo step 4 heating zones 3 & 6 asoako step 5 heating zones 4 & 7 aspikeo step 6 vent step 7 cooling 200 c 150 c 100 c 5 c time (3 to 7 minutes total) t max solder is liquid for 40 to 80 seconds (depending on mass of assembly) 205 to 219 c peak at solder joint desired curve for low mass assemblies desired curve for high mass assemblies 100 c 150 c 160 c 170 c 140 c figure 15. typical solder heating profile
mmdf2c01hd http://onsemi.com 13 package dimensions style 14: pin 1. nsource 2. ngate 3. psource 4. pgate 5. pdrain 6. pdrain 7. ndrain 8. ndrain seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 x y g m y m 0.25 (0.010) z y m 0.25 (0.010) z s x s m xxxxxx alyw so8 case 75107 issue v
mmdf2c01hd http://onsemi.com 14 notes
mmdf2c01hd http://onsemi.com 15 notes
mmdf2c01hd http://onsemi.com 16 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mmdf2c01hd/d minimos is a trademark of semiconductor components industries, llc (scillc). thermal clad is a registered trademark of the bergquist company. north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland

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